The present invention relates to a method of regulating locally the voltages at the drain and body terminals of a non-volatile memory cell being programmed. More particularly, the invention relates to a method of regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed, wherein the voltages are applied through a program-load circuit connected in a conduction pattern for transferring a predetermined voltage value to at least one terminal of the memory cell. The invention further relates to a program-load circuit connected in a semiconductor-integrated electronic memory device that comprises a non-volatile memory cell array, with each memory cell including at least one floating gate transistor formed with source, drain, gate, and body terminals, the program-load circuit being connected in a conduction pattern for transferring a predetermined voltage value to a terminal of the memory cell.
As is well known in this technical field, a pressing demand of a world-wide semiconductor market for high-density non-volatile memories, e.g., flash EEPROMs, has led to so-called xe2x80x9cmulti-levelxe2x80x9d memory devices being developed in which each memory cell can store more than one bit. Each bit is associated with a predetermined logic level, and the levels have been made identifiable by providing the memory cell with a plurality of threshold voltages. A skilled person in the art will surely appreciate that, as the number of threshold voltage levels increases, the requirements become stricter with regards to proper performance of the operations to be carried out on the cells, such as the erase, program, and read operations.
For a reliability reason, the voltage range available for assigning the 2nxe2x88x921 distributions (all of them but the most programmed one) of a multi-level non-volatile memory having n bits per cell lies below 4.5 to 5 V. As a result, both the widths of the threshold distributions and the gaps between them have to be reduced. FIG. 1 of the accompanying drawings represents the distribution of threshold voltages of a conventional two-level (two bits per cell) memory cell compared to that of a multi-level memory having three bits per cell. Thus, a set of phenomena should be taken into account in the fabrication of multi-level memory devices which are instead immaterial to conventional flash memories.
A review of how the programming steps proceed in multi-level flash memories may be of assistance toward a better understanding of the features of the invention. Writing into a flash cell includes varying the threshold voltage of the cell to an appropriate extent by storing electrons into its floating gate region. FIG. 2 shows some straight lines representing the characteristic relationship that exists between the voltage applied to the gate terminal of the memory cell and the threshold jump produced by the voltages applied to the drain terminal of the cell being changed.
To program the cell, and obtain distributions of threshold voltages that are adequately accurate for the multi-level mode of operation, the voltage applied to the control gate terminal is varied stepwise between a minimum and a maximum value. The width of the voltage step is the threshold jump being sought, with the drain terminal under optimum conditions. Completing the programming operation by a stepped gate voltage brings about a timing problem, whereby programming time can be reduced or minimized by having a large number of cells programmed in parallel. Parallel programming may be performed using a xe2x80x9cProgram and Verifyxe2x80x9d algorithm. As this algorithm is being executed, each program pulse is followed by an operation of reading from the cells being programmed to check that the cells have reached their threshold values.
A properly programmed cell will receive no further program pulses, whereas any cells that are still below the desired threshold value are re-programmed by the same algorithm. For this purpose, program-load circuits are employed, by applying to the drain terminals of the cells to be programmed, predetermined program voltage values. An example of these program-load circuits is shown schematically in FIG. 3.
The number of program-load circuits provided matches the parallel programming; for example, 64 program-load circuits would be provided where 64 cells are to be programmed in parallel. Each program-load circuit is supplied a voltage VPD from a voltage booster or a charge pump DRAIN PUMP. The charge pump outputs a voltage value PDOUT, which is then regulated through a drain voltage regulator such that the supply value VPD will be as stable and accurate as possible. Shown schematically in FIG. 4 are sequential functional blocks responsible for generating the supply voltage VDP.
Let us review now some of the problems involved in programming flash cells with two or more bits per cells. Represented in FIG. 5 is a practical example of the positioning of circuit portions connected to the drain terminals of the cells, and of circuit portions arranged to generate the program voltage, in the layout of an electronic memory device. It can be appreciated from this diagram that the charge pump and the regulator lie fairly close to each other, and that the voltage VPD produced will be routed, over metallization lines, to program-load circuits located in proximity to the logic circuit portions used for driving them. The outputs of these program-load circuits are further connected, as by metal routing connections and through column decoding blocks, to the drain terminals of the cells, as FIG. 6 shows in greater detail.
Program-load circuits are clustered in the electronic device layout such that the routing connections between the program-load circuit outputs and the drain terminals of the cells to be programmed can be kept as uniform as possible. However, this only holds true in an ideal case of the output resistance of the voltage regulator being zero. Anyhow, it has been common practice to have the I/O logic circuit portions situated at opposed positions in the electronic device. On this account, a parasitic resistance value Rpar, introduced by the routing connections from the supply VPD, is not to be ignored. This parasitic resistance has the effect of supplying, instead of the voltage VPD, a voltage value VPDxe2x80x2 which is a function of the current that flows through the parasitic resistor Rpar.
By definition, a variation in the current demanded from the voltage regulator will not alter its output voltage, at least not in the ideal case. The supply voltage VPD can therefore be considered a constant value as the load varies. It can thus be appreciated that the other voltage, VPDxe2x80x2, is a design function of the program-load circuits or, stated otherwise, of the conduction patterns that are associated with the programming operation.
An attempt to address the problem of this variation in drain voltage during the programming step should take into close consideration the routing connections to the voltage VPD, if the parasitic resistance Rpar is to be reduced or minimized. However, this possible course is made inadequate since the metal connections to the reference supply voltages VPD cannot be expanded indefinitely, due to constraints established by the layout of the electronic device. In addition, an increase in parallel programming would act against addressing the problem, because the current through the parasitic resistor Rpar would also increase.
In view of the foregoing background, it is therefore an object of the invention to provide a method for stabilizing the voltages at the drain and body terminals of a multi-level non-volatile memory cell during the cell programming step, which significantly decreases the effects of the parasitic resistors that appear at the interconnections between the supply voltage sources and the circuit portions arranged to be supplied therefrom.
The invention provides a local regulation of the drain voltage at the programming step, by multiplying the last stage of the drain regulator by the number of program-load circuits provided in the electronic device and shifting the stage to a location closer to each of the circuits.